1. Field of the Invention
The present invention relates to an output circuit of a semiconductor integrated circuit.
2. Description of the Related Art
As the demand for improved an operation speed and a lowering of the power consumption of computers increases, a higher speed and less use of power are required from semiconductor integrated circuits to meet these requirements, a combination of a TTL and Bi-CMOS circuit composed of CMOSs is now under consideration. The speed can be further improved by using a combination of an ECL and a Bi-CMOS circuit.
FIG. 3 shows a simple combination of a Bi-CMOS circuit and ECL according to the prior art. In the figure, MP1 denotes a p-channel MOS transistor and MN1 an n-channel MOS transistor, and these transistors and resistors R1 and R2 are connected in series between power sources VCC (0 V) and VEE (-5.2 V). NPN bipolar transistors Q1 and Q2 are connected in series between the power sources VCC and VEE, and the resistors R1 and R2 produce base-emitter voltages of the bipolar transistors Q1 and Q2. These elements form the Bi-CMOS circuit.
The ECL comprises npn bipolar transistors Q3 and Q4, load resistors R3 and R4, and a constant current source including an npn transistor Q5 and a resistor R5. A base of the transistor Q3 is connected to an output end "a" of the Bi-CMOS circuit, a base of the transistor Q4 receives a reference voltage VBB1, and an output of the ECL is picked up from collectors of the transistors Q3 and Q4. In the example of FIG. 3, the output of the ECL is picked up from one collector "b" of the respective collectors of transistors Q3 and Q4 and is applied to a base of an npn transistor Q6 of an emitter follower. A diode Q7 is reversely connected between the power source VCC and an output end OUT, to protect the transistor Q6.
When an input IN is high (H), the MP1 is made OFF, the MN1 is made ON, the Q1 is made OFF, and the Q2 is made ON, and thus the output end a of the Bi-CMOS is made low (L). When the input IN is L, the MP1 is made ON, the MN1 is made OFF, the Q1 is made ON, and the Q2 is made OFF, and thus the output end a is made H. Accordingly, the levels H and L of the input IN are inverted to become levels L and H at the output end a of the Bi-CMOS circuit (a Bi-CMOS inverter); at the output end a, the level H is about VCC (nearly 0 V) and the level L is about VEE (nearly -5.2 V).
The H=VCC and L=VEE signals are improper as input signals for the ECL, because the proper inputs for the ECL are usually VIH=-0.9 V and VIL=-1.8 V. Assuming the output OUT of the ECL is -0.9 V for a level H and -1.8 V for a level L, a potential at the node b will be -0.1 V for the level H and -1.0 V for the level L if a base-emitter voltage VBE of the transistor Q6 which is added to the level of the node b, is 0.8 V. When the Bi-CMOS circuit provides a signal amplitude of VIH=VCC=0 V and VIL=VEE=-5.2 V, a base voltage (0 V) of the transistor Q3 becomes higher than its collector voltage (-1.0 V) when the node a is level H (with VIH), and thus the transistor Q3 may be saturated.
Further, the reference voltage VBB1 applied to the base of the transistor Q4 is usually -1.3 V, and thus VEE (-5.2 V) at the node a for the level L is too low, which may cause problems for the withstand voltage of the transistor Q3. Namely, common emitter voltage of the transistors Q3 and Q4 is VBB1-VBE, and therefore, a voltage of VEE-VBB1+VBE is applied as a reverse bias voltage between the base and emitter of the transistor Q3, thereby setting the transistor Q3 to a reverse-biased state.
FIG. 4 shows another prior art circuit which solves the problem of too high an amplitude of the output of the Bi-CMOS. In this example, diodes Q8 and Q9 and a Schottky diode SD1 clamp level L of an output node "a", and the resistor R1 of FIG. 3, are removed to lower the level H of the node a.
When an input IN is high (H) in FIG. 4, the MP1 is made OFF, the Q1 is made OFF, the MN1 is made ON, and the MN2 is made ON, and accordingly, a transistor Q2 is turned ON through a path Q8, Q9, SD1, R6, and MN2, which supplies a base current to the transistor Q2. The logic signal level at the output node a is an L of about -2.0 V, which is lower than VCC by the amount of a voltage produced by Q8, Q9, and SD1.
When the input IN is low (L), the MP1 is made ON, the Q1 is made ON, MN1 and MN2 are made OFF, and Q2 is made OFF, and thus the output node a will have an H of about -0.8 V, which is lower than VCC by the base-emitter voltage VBE of the transistor Q1. The H and L levels of -0.8 V and -2.0 V are proper for a reference voltage VBB1 of -1.3 V.
Similar to the example of FIG. 3, it is assumed that the levels H and L of an output OUT of FIG. 4 are VOH=-0.9 V and VOL=-1.8 V, and that the levels H and L at a node "b" are -0.1 V and -1.0 V, which are higher than the levels of the output OUT by a base-emitter voltage VBE=0.8 V of the transistor Q6. At a level H, the base of the transistor Q3 is -0.8 V and the collector thereof -0.1 V, and thus the collector voltage cannot fall below the base voltage. Also at a level L, the transistor Q3 presents an emitter voltage of VBB1-VBE =-2.1 V and a base voltage of -2.0 V, and thus a reverse bias voltage cannot be applied between the base and the emitter. As a result, no problem occurs with the withstand voltage of the transistor Q3.
In FIG. 3, the level H of the output node a substantially reaches VCC because of the resistor R1, and if this resistor is removed, the level can be lowered by the VBE of the voltage transistor Q1. The resistor R1 is necessary, however, for supplying a base current to the transistor Q1, and the resistor R2 is necessary for turning ON the transistor Q2; if the resistors R1 and R2 are removed, it is necessary to provide another circuit for supplying base currents to the transistors Q1 and Q2, and this is why the circuits of FIGS. 3 and 4 have different Bi-CMOS's. In FIG. 4, the base current to the transistor Q1 is supplied through MP1, Q1, Q3, and Q5, and the base current to the transistor Q2 is supplied through Q8, Q9, SD1, R6, and MN2.
The resistors R1 and R2 also function to the bases of the transistors Q1 and Q2 when turning OFF these transistors. In FIG. 4, the transistor MN1 discharges the base of the transistor Q1, and a resistor R7 discharges the base of the transistor Q2 (the resistor R7 is identical to the resistor R2).
As explained above, the example of FIG. 3 provides an excessive amplitude from the Bi-CMOS circuit, thereby saturating the bipolar transistors of the ECL, extending a delay time, and causing a problem with the withstand voltage of the transistors, and thus the circuit of FIG. 3 is not practical.
Further, the diode clamping technique of FIG. 4 may suppress and properly set an input voltage of the ECL, but it consumes unnecessary electric power because a current passes through a path Q8, Q9, SD1, R6, and Q2, and thus the circuit of FIG. 4 cannot satisfy the requirement for a low power consumption.